Adder (electronics)
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An adder is a digital circuit that performs addition of numbers. In many computers and other kinds of processors adders are used in the arithmetic logic units or ALU. They are also used in other parts of the processor, where they are used to calculate addresses, table indices, increment and decrement operators and similar operations.
Although adders can be constructed for many number representations, such as binarycoded decimal or excess3, the most common adders operate on binary numbers. In cases where two's complement or ones' complement is being used to represent negative numbers, it is trivial to modify an adder into an adder–subtractor. Other signed number representations require more logic around the basic adder.
Contents
Binary adders[edit]
Half adder[edit]
The half adder adds two single binary digits A and B. It has two outputs, sum (S) and carry (C). The carry signal represents an overflow into the next digit of a multidigit addition. The value of the sum is 2C + S. The simplest halfadder design, pictured on the right, incorporates an XOR gate for S and an AND gate for C. The Boolean logic for the sum (in this case S) will be A′B + AB′ whereas for the carry (C) will be AB. With the addition of an OR gate to combine their carry outputs, two half adders can be combined to make a full adder.^{[1]} The half adder adds two input bits and generates a carry and sum, which are the two outputs of a half adder. The input variables of a half adder are called the augend and addend bits. The output variables are the sum and carry. The truth table for the half adder is:
Inputs Outputs A B C S 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1 0
Full adder[edit]
A full adder adds binary numbers and accounts for values carried in as well as out. A onebit fulladder adds three onebit numbers, often written as A, B, and C_{in}; A and B are the operands, and C_{in} is a bit carried in from the previous lesssignificant stage.^{[2]} The full adder is usually a component in a cascade of adders, which add 8, 16, 32, etc. bit binary numbers. The circuit produces a twobit output. Output carry and sum typically represented by the signals C_{out} and S, where the sum equals 2C_{out} + S.
A full adder can be implemented in many different ways such as with a custom transistorlevel circuit or composed of other gates. One example implementation is with S = A ⊕ B ⊕ C_{in} and C_{out} = (A ⋅ B) + (C_{in} ⋅ (A ⊕ B)).
In this implementation, the final OR gate before the carryout output may be replaced by an XOR gate without altering the resulting logic. Using only two types of gates is convenient if the circuit is being implemented using simple integrated circuit chips which contain only one gate type per chip.
A full adder can also be constructed from two half adders by connecting A and B to the input of one half adder, then taking its sumoutput S as one of the inputs to the second half adder and C_{in} as its other input, and finally the carry outputs from the two halfadders are connected to an OR gate. The sumoutput from the second half adder is the final sum output (S) of the full adder and the output from the OR gate is the final carry output (C_{out}). The critical path of a full adder runs through both XOR gates and ends at the sum bit s. Assumed that an XOR gate takes 1 delays to complete, the delay imposed by the critical path of a full adder is equal to
The critical path of a carry runs through one XOR gate in adder and through 2 gates (AND and OR) in carryblock and therefore, if AND or OR gates take 1 delay to complete, has a delay of
The truth table for the full adder is:
Inputs Outputs A B C_{in} C_{out} S 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1
Adders supporting multiple bits[edit]
Ripplecarry adder[edit]
It is possible to create a logical circuit using multiple full adders to add Nbit numbers. Each full adder inputs a C_{in}, which is the C_{out} of the previous adder. This kind of adder is called a ripplecarry adder (RCA), since each carry bit "ripples" to the next full adder. Note that the first (and only the first) full adder may be replaced by a half adder (under the assumption that C_{in} = 0).
The layout of a ripplecarry adder is simple, which allows fast design time; however, the ripplecarry adder is relatively slow, since each full adder must wait for the carry bit to be calculated from the previous full adder. The gate delay can easily be calculated by inspection of the full adder circuit. Each full adder requires three levels of logic. In a 32bit ripplecarry adder, there are 32 full adders, so the critical path (worst case) delay is 3 (from input to carry in first adder) + 31 × 2 (for carry propagation in latter adders) = 65 gate delays.^{[3]} The general equation for the worstcase delay for a nbit carryripple adder, accounting for both the sum and carry bits, is
A design with alternating carry polarities and optimized ANDORInvert gates can be about twice as fast.^{[4]}
Carrylookahead adder[edit]
To reduce the computation time, engineers devised faster ways to add two binary numbers by using carrylookahead adders (CLA). They work by creating two signals (P and G) for each bit position, based on whether a carry is propagated through from a less significant bit position (at least one input is a 1), generated in that bit position (both inputs are 1), or killed in that bit position (both inputs are 0). In most cases, P is simply the sum output of a half adder and G is the carry output of the same adder. After P and G are generated, the carries for every bit position are created. Some advanced carrylookahead architectures are the Manchester carry chain, Brent–Kung adder (BKA),^{[5]} and the Kogge–Stone adder (KSA).^{[6]}^{[7]}
Some other multibit adder architectures break the adder into blocks. It is possible to vary the length of these blocks based on the propagation delay of the circuits to optimize computation time. These block based adders include the carryskip (or carrybypass) adder which will determine P and G values for each block rather than each bit, and the carryselect adder which pregenerates the sum and carry values for either possible carry input (0 or 1) to the block, using multiplexers to select the appropriate result when the carry bit is known.
By combining multiple carrylookahead adders, even larger adders can be created. This can be used at multiple levels to make even larger adders. For example, the following adder is a 64bit adder that uses four 16bit CLAs with two levels of LCUs.
Other adder designs include the carryselect adder, conditional sum adder, carryskip adder, and carrycomplete adder.
Carrysave adders[edit]
If an adding circuit is to compute the sum of three or more numbers, it can be advantageous to not propagate the carry result. Instead, threeinput adders are used, generating two results: a sum and a carry. The sum and the carry may be fed into two inputs of the subsequent 3number adder without having to wait for propagation of a carry signal. After all stages of addition, however, a conventional adder (such as the ripplecarry or the lookahead) must be used to combine the final sum and carry results.
3:2 compressors[edit]
A full adder can be viewed as a 3:2 lossy compressor: it sums three onebit inputs and returns the result as a single twobit number; that is, it maps 8 input values to 4 output values. Thus, for example, a binary input of 101 results in an output of 1 + 0 + 1 = 10 (decimal number 2). The carryout represents bit one of the result, while the sum represents bit zero. Likewise, a half adder can be used as a 2:2 lossy compressor, compressing four possible inputs into three possible outputs.
Such compressors can be used to speed up the summation of three or more addends. If the addends are exactly three, the layout is known as the carrysave adder. If the addends are four or more, more than one layer of compressors is necessary, and there are various possible designs for the circuit: the most common are Dadda and Wallace trees. This kind of circuit is most notably used in multipliers, which is why these circuits are also known as Dadda and Wallace multipliers.
See also[edit]
 Subtractor
 Electronic mixer — for adding analog signals
References[edit]
 ^ Lancaster, Geoffrey A. (2004). Excel HSC Software Design and Development. Pascal Press. p. 180. ISBN 9781741251753.
 ^ Mano, M. Morris (1979). Digital Logic and Computer Design. PrenticeHall. pp. 119–123. ISBN 9780132145107.
 ^ Satpathy, Pinaki (2016). Design and Implementation of Carry Select Adder Using TSpice. Anchor Academic Publishing. p. 22. ISBN 9783960670582.
 ^ Burgess, Neil (2011). Fast RippleCarry Adders in StandardCell CMOS VLSI. 20th IEEE Symposium on Computer Arithmetic. pp. 103–111.
 ^ Brent, Richard Peirce; Kung, Hsiang Te (March 1982). "A Regular Layout for Parallel Adders". IEEE Transactions on Computers. C31 (3): 260–264. doi:10.1109/TC.1982.1675982. ISSN 00189340.
 ^ Kogge, Peter Michael; Stone, Harold S. (August 1973). "A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations". IEEE Transactions on Computers. C22 (8): 786–793. doi:10.1109/TC.1973.5009159.
 ^ Reynders, Nele; Dehaene, Wim (2015). Written at Heverlee, Belgium. UltraLowVoltage Design of EnergyEfficient Digital Circuits. Analog Circuits and Signal Processing Series. Analog Circuits And Signal Processing (ACSP) (1 ed.). Cham, Switzerland: Springer International Publishing AG Switzerland. doi:10.1007/9783319161365. ISBN 9783319161358. ISSN 1872082X. LCCN 2015935431.
Further reading[edit]
 Liu, TsoKai; Hohulin, Keith R.; Shiau, LihEr; Muroga, Saburo (January 1974). "Optimal OneBit FullAdders with Different Types of Gates". IEEE Transactions on Computers. Bell Laboratories: IEEE. C23 (1): 63–70. doi:10.1109/TC.1974.223778. ISSN 00189340.
 Lai, Hung Chi; Muroga, Saburo (September 1979). "Minimum Binary Parallel Adders with NOR (NAND) Gates". IEEE Transactions on Computers. IEEE. C28 (9): 648–659. doi:10.1109/TC.1979.1675433.
 Mead, Carver; Conway, Lynn (1980) [December 1979]. Introduction to VLSI Systems (1 ed.). Reading, MA, USA: AddisonWesley. Bibcode:1980aw...book.....M. ISBN 9780201043587. Retrieved 20180512.
 Davio, Marc; Dechamps, JeanPierre; Thayse, André (1983). Digital Systems, with algorithm implementation (1 ed.). Philips Research Laboratory, Brussels, Belgium: John Wiley & Sons, a WileyInterscience Publication. ISBN 9780471104131. LCCN 822710.
External links[edit]
 Hardware algorithms for arithmetic modules, includes description of several adder layouts with figures.
 8bit Full Adder and Subtractor, a demonstration of an interactive Full Adder built in JavaScript solely for learning purposes.
 Interactive Full Adder Simulation (requires Java), Interactive Full Adder circuit constructed with Teahlab's online circuit simulator.
 Interactive Half Adder Simulation (requires Java), Half Adder circuit built with Teahlab's circuit simulator.
 4bit Full Adder Simulation built in Verilog, and the accompanying Ripple Carry Full Adder Video Tutorial